1. Field of the Invention
The present invention relates to a microwave semiconductor switch adapted to switch the transmission path for microwaves depending on whether the power of the applied electric wave is large or small.
2. Description of the Prior Art
FIGS. 1(a) and 1(b) are plan and side elevation, respectively, that show the constitution of a microwave semiconductor switch which is shown in "IEEE Transactions on ED", Vol. ED-28, No. 2, February 1981 "Resonated GaAs FET Devices for Microwave Switching". In the drawing, numeral 1 designates a semiconductor substrate, numeral 2 designates the first microstrip line (microstrip lines are hereinafter referred to simply as lines), numeral 3 designates the second line, numeral 4 designates the third line, numerals 5 and 6 designate respective inductor lines, numerals 7 and 8 designate gate bias lines and numeral 9 designates the ground plate. The ground plate 9 is constituted by metalizing a conductor at the rear surface of semiconductor substrate 1. The first, second and third lines have an electrostatic capacity distributed relative to the ground plate 9. The microwave voltage propagates along said lines as the voltage between the lines and the ground plate.
Numeral 10 designates the first field effect transistor (herinafter abbreviated to FET), numeral 11 designates the drain electrode of FET 10, numeral 12 designates the source electrode of FET 10, numeral 13 designates the gate electrode of FET 10, numeral 14 designates the second FET, numeral 15 designates the drain electrode of FET 14, numeral 16 designates the source electrode of FET 14 and numeral 17 designates the gate electrode of FET 14.
One end of the first line 2 is connected to the input/output terminal and the other end is bifurcated. The two branches are respectively connected to the source electrodes 12, 16 of the first and second FETs. It is further to be noted that the drain electrode 11 of the first FET 10 is connected to the second line 3 and that the drain electrode 15 of the second FET 14 is connected to the third line 4. The bias voltage is applied to the gate electrode 13 of the first FET 10 and the gate electrode 17 of the second FET through the gate bias lines 7, 8 respectively. The source electrodes and the drain electrodes of the first FET 10 and the second FET 14 are at the same potential with respect to D.C. bias and the high impedance line 18 having the tip end connected to the ground plate 9 is connected to the main lines so as to make the potential of the main lines the same as that of the ground plate 9.
Referring to FIG. 2 showing an equivalent circuit having the connections shown in FIG. 1, the same numerals as those employed in FIGS, 1(a) and 1(b) designate similar portions.
Operation of the microwave semiconductor switch shown in FIGS. 1(a) and 1(b) will next be explained. The potential at the ground plate 9 (i.e. voltage is zero) is applied to the gate electrode 13 and the gate electrode 17 has the bias voltage V.sub.BIAS (.vertline.V.sub.BIAS .vertline.&gt;.vertline.Vp.vertline.) which is lower than the pinch-off voltage Vp applied to it. Low impedance R is caused relative to the microwave voltage between the source electrode 12 and the drain electrode 11, and the connection between the source electrode 16 and the drain electrode 15 is cut off so that a capacitive impedance JX.sub.2 is caused relative to the microwave. This impedance JX.sub.2 is connected in parallel with the impedance caused by the inductance line 6 and parallelly-resonated relative to the microwave frequency so that a high impedance is provided. Accordingly, the first line 2 and second line 3 is connected relative to the microwave but the connection between the first line 2 and the third line 4 is cut off.
Similarly, if the potential of zero V is applied to the gate electrode 17 and V.sub.BIAS to the gate electrode 13, the first line 2 and the third line 4 are connected but the connection between the first line 2 and the second line 3 is cut off.
Since a microwave semiconductor switch according to the prior art is so constituted, the breakdown voltage of field effect transistors will become problematical. For example, assuming that the characteristic impedance of the respective microstrip lines is Z, and that the input power is P, FET 14 being cut-off and the input power P being transmitted from the first line 2 to the second line 3 withuut generating any standing wave, the effective value Ve of the voltage between the first line and the ground plate 9 is Ve=.sqroot.PZ which will become the voltage at the source electrode 16. The maximum value of this voltage is 1.4 Ve. On the other hand, since the gate electrode 17 is applied with V.sub.BIAS, the maximum voltage as applied between the gate electrode and the source electrode is ##EQU1## which is 13.6 V if it is assumed, for example, that V.sub.BIAS =-5 V, Z=50 .OMEGA., and P=3 W. It is not easy, however, to obtain a high breakdown voltage of more than 13.6 V between the gate electrode and the source electrode in FETs intended to serve as switches having a low loss and a small resistance R.sub.1 between the drain electrode and the source electrode under the ON state while keeping the gate bias voltage at zero V. The production efficiency of FETs having high breakdown voltage characteristics is therefore poor so that very expensive microwave semiconductor switches may result.
FIGS. 3(a) and 3(b) are a plane view and side elevation respectively illustrating another example of the construction of microwave semiconductor switches as presented in the technical papers reported at the Symposium "IEEE 1982 Microwave and Millimeter-Wave Monolithic Circuits Symposium" held in U.S.A. in June, 1982.
In FIG. 3(a), numeral 19 designates the second input/output line, numeral 20 designates the third input/output line, numeral 21 designates a low impedance line having a length equivalent to one half of the wave length, and numeral 22 designates a high impedance line having a length equivalent to one half of the wave length. These microstrip lines are formed on the semiconductor substrate 1 (shown in FIG. 3(b)).
Numeral 23 designates the first field effect transistor (hereinafter abbreviated as the first FET), numeral 24 designates the drain electrode of the first FET, numeral 25 designates the source electrode of the first FET, and numeral 26 designates the gate electrode of the first FET. The source electrode 25 of the second FET is connected to the ground plate 9 through golden wires 27 or the like, and the drain electrode 24 of the first FET is connected to the low impedance line 21.
Numeral 28 designates the second field effect transistor (hereinafter abbreviated as the second FET), numeral 29 designates the drain electrode of the second FET, numeral 30 designates the source electrode of the second FET and numeral 31 designates the gate electrode of the second FET. The source electrode 30 of the second FET is connected to the ground plate 9 through golden wires 27 or the like and the drain electrode 29 of the second FET is connected to the high impedance line 22.
A bias voltage is applied to the gate electrode 26 of the first FET 23 from the first bias terminal 33 through the bias circuit 32 comprising microstrip line. Similarly, a bias voltage is applied to the gate electrode 31 of the second FET 28 from the second bias terminal 34 through the bias circuit 32.
The point where the first input/output line 2, the low impedance line 21 and the high impedance line 22 are connected to each other is termed the junction point 35. Then the drain electrodes of the first FET 23 and the second FET 28 are connected at a point on the low impedance line 21 and high impedance line 22 that is spaced one quarter of the wave length from the junction point 35, respectively
In order that the source electrodes and the drain electrodes of both FETs be placed at the same potential, the high impedance ground line 36 is connected from the ground plate 9 to the first input/output line 2. High impedance ground line 36 therefore causes the input/output line 2 to be grounded with respect to D.C. current. However, because line 36 presents a high impedance to microwave signals in the normal operating range, it does not ground input/output line 2 with respect to such microwave signals.
Operation of the switch will next be explained.
FIG. 4 illustrates a circuit equivalent to that shown in FIGS. 3(a) and 3(b) for explanation of the operation of the microwave semiconductor switch shown in FIGS. 3(a) and 3(b). In this equivalent circuit diagram, the bias circuit 32 and the high impedance ground line 36 are omitted for the sake of simplicity.
Explanation on the operation of the switch with reference to FIG. 4 proceeds firstly with the case where a low power microwave has been provided from the first input/output line 2 and then with the case where a high power microwave with a power on the order of several watts has been provided.
Firstly, it is assumed that the low power microwave has been supplied from the first input/output line 2 and propagates to the third input/output line 20.
At this time, a negative bias voltage V.sub.BIAS (.vertline.V.sub.BIAS .vertline.&gt;.vertline.Vp.vertline.) smaller than the pinch-off voltage Vp is applied t.o the second bias terminal 34 and the second FET 28 provides a high impedance. At the same time, the first bias terminal 33 is placed at zero V and the first FET 23 provides a low impedance, which is referred to as R.sub.1. Since this impedance R.sub.1 is sufficiently smaller than the characteristic impedance Z.sub.1 of the low impedance line 21, the impedance as viewed from the junction point 35 to the second input/output line 19 shows as high impedance as an almost fully opened condition. Accordingly, the microwave provided from the first input/output line 2 propagates along the high impedance line 22 and appears at the third input/output line 20. At this instance since the second FET 28 provides a high impedance, the microwave being propagated will not be affected
Next, consideration is given to the case in which a high power microwave is provided from the first input/output line 2 and the microwave is supplied to the second input/output line 19. In this case, the conditions of the bias applied to FETs is assumed to be as follows The second bias terminal 34 is placed at zero V and a negative bias voltage V.sub.BIAS (.vertline.V.sub.BIAS .vertline.&gt;.vertline.Vp.vertline.) smaller than the pinch-off voltage Vp is applied to the first bias terminal 32. Under this biasing condition, the second FET 28 provides a low impedance R.sub.2 and the first FET 23 provides a high impedance. Consequently, the impedance as viewed from the junction point 35 to the third input/output lines 20 shows as high impedance as an almost fully opened condition and the microwave provided from the first input/output line propagates along the low impedance line 21 and appears at the second input/output line 19.
It is to be noted here that the first FET 23 provides a high impedance and will not affect the microwaves propagating along the low impedance line 21 having the characteristic impedance Z.sub.1.
In the switch under such biasing conditions, since the high power microwave propagates, the RF current which flows through the second FET 28 and the RF voltage applied to the first FET 23 both have large values. It is therefore necessary to use FETs capable of standing these large values.
If a microwave having a power of P watt is assumed to have been input, RF Peak current I which flows through the second FET 28 may be expressed by the following equation: ##EQU2## where R.sub.2 is the resistance of the second FET 28 biased at zero V and Z.sub.2 is the characteristic impedance of the high impedance line 22.
In the meantime( RF Peak voltage V which is applied to the first FET 23 may be expressed by the following equation: ##EQU3## where Z.sub.1 is the characteristic impedance of the low impedance line 21.
For example, assuming that the input/output power is equal to 5 W, Z.sub.0 =50 .OMEGA., R.sub.2 =3 .OMEGA. and that Z.sub.2 is equal to 75 .OMEGA., Z.sub.1 being equal to 40 .OMEGA., the value of the current is 0.23 A and the value of the voltage V is 14 V. As far as the current value of 0.23 A is concerned, this value will be a drain current which can be caused to flow by FETs having a normal gate width of 1 mm and there is not problem. However, with regard to the voltage, the value 14 V is one which may possibly exceed the permissible value for FETs. In other words, if the gate bias voltage of the first FET 23 is assumed to be V.sub.BIAS, the pinch-off voltage being assumed to be Vp and the break-down voltage at the gate being assumed to be V.sub.BR, the following relationships have to be established: ##EQU4##
If the absolute value of the pinch-off voltage .vertline.Vp.vertline. is assumed to be equal to 2 V, 16 V is required for the breakdown voltage .vertline.V.sub.BR .vertline. and 9 V is required for the bias voltage .vertline.V.sub.BIAS .vertline.. This breakdown voltage of 16 V cannot be so easily obtained by the sort of FETs which are designed for mass-production, and it is also difficult to make the allowable input power to microwave semiconductor switches of this sort to be on the order of 3 W.
Moreover, in order to reduce the voltage applied to the FETs, the electrical length of the low impedance line 21 should be chosen to be equal to one half of the wave length, which causes the area of the semiconductor substrate 1 constituting this microwave semiconductor switch to be increased.
Since the microwave semiconductor switch shown in FIGS. 3(a) and 3(b) is constructed in the manner explained above, in order to enable an increase in the permissible input power to a level of several watts, a production method involving special steps for manufacturing FETs which are highly resistant against high voltages has to be employed, and this has resulted in such problems as reduction in production efficiency and unsuitability for mass-production. At the same time, since a low impedance line having a length equivalent to one half of the wave length is employed which does not permit high voltages to be applied to the FETs, the dimensions of the semiconductor substrate have to be increased.